BINARY SUBTRACTION

Binary subtraction

   is simplified as well, as long as we remember how subtraction and the base 2 number system. Let's first look at an easy example.

  111

 - 10

  101

Note that the difference is the same if this was decimal subtraction. Also similar to decimal subtraction is the concept of "borrowing." Watch as "borrowing" occurs when a larger digit, say 8, is subtracted from a smaller digit, say 5, as shown below in decimal subtraction.

    35

  -   8

    27

For 10 minus 1, 1 is borrowed from the "tens" column for use in the "ones" column, leaving the "tens" column with only 2. The following examples show "borrowing" in binary subtraction.

    10       100      1010

   -  1       - 10     - 110

      1          10       100

BINARY SUBTRACTOR

HALF SUBTRACTOR

The half-subtractor is a combinational circuit which is used to perform subtraction of two bits. It has two inputs, A (minuend) and Y (subtrahend) and two outputs D (difference) and B (borrow).

It is an arithmetic circuit that subtracts one bit from the other. It is used to subtract the LSB of the subtrahend from the LSB of the minuend when a binary number is to be subtracted from the other. A logic circuit is called half adder which accepts two binary digits as its input and produces two binary digits on its output terminals known as difference bit and borrow bit. 

From the above table one can draw the karnaugh map for "difference" and "borrow".

So, Logic equations are:

From these two expression implementation requirement for a half subtractor function requires one Ex-OR gate for Difference generation and an AND gate with a NOT gate for Borrow generation.  

FULL SUBTRACTOR

A full subtractor is a combinational digital circuit that is used to carry out subtraction involving three bits. This circuitry is then used in a cascade arrangement to synthesize multiple bit subtractor circuits. There are three input and two output bits that are involved in an nth bit full subtractor circuit  

Logic equations are:

BINARY ADDITION 

Binary addition

   works in the same way, except that only 0's and 1's can be used, instead of the whole spectrum of 0-9. This actually makes binary addition much simpler than decimal addition, as we only need to remember the following:

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 10

As an example of binary addition we have,

  101

+101

a) To add these two numbers, we first consider the "ones" column and calculate 1 + 1, which (in binary) results in 10. We "carry" the 1 to the "tens" column, and the leave the 0 in the "ones" column.

b) Moving on to the "tens" column, we calculate 1 + (0 + 0), which gives 1. Nothing "carries" to the "hundreds" column, and we leave the 1 in the "tens" column.

c) Moving on to the "hundreds" column, we calculate 1 + 1, which gives 10. We "carry" the 1 to the "thousands" column, leaving the 0 in the "hundreds" column.

  101

+101

1010

Another example of binary addition:

  1011

+1011

10110

Note that in the "tens" column, we have 1 + (1 + 1), where the first 1 is "carried" from the "ones" column. Recall that in binary,

1 + 1 + 1 = 10 + 1

                = 11

BINARY ADDERS

An arithmetic circuit which is a combination circuit that performs arithmetic operations such as addition and subtraction with binary numbers or with decimal numbers in a binary code. 

HALF ADDER

It is an arithmetic circuit that generates the sum of two binary digits. The circuit has two inputs and to outputs. The input variables are augend and addend bits to be added, and the output variables produce the sum and carry.  

The C output is 1 only when both outputs are 1. The S output are least significant bit of the sum. The Boolean functions for the two outputs, easily obtained from the truth table are

S = X’Y + XY’= X+Y

C = XY

The half adder can be implemented with one exclusive OR gate and one AND gate.

A half-adder adds two 1-bit inputs and produces a sum bit and a carry bit as outputs. 

FULL ADDER

A full adder is a combinational circuit that forms the arithmetic sum of three input bits. Besides the tree inputs, it has two outputs. Two of the iput variables denoted by A and B, present the two significant bits to be added. The third input, C(Carry In), represents the carry from the previous lower significant position. Two outputs are necessary because the arithmetic sum of three bits ranges from 0 to 3, and binary 2 and 3 need two digits for their representation. Again, the two outputs are designated by the symbol S for “sum” and C for “carry”; the binary variable S gives the value of the bit of the sum, and the binary variable C gives the output carry. 

A full-adder is merely a half-adder that accepts an extra input; namely, the carry bit from another full-adder. Each full-adder is responsible for adding one pair of corresponding digits from the two numbers to be added, and it must add to that the carry bit from the previous full-adder. The full-adder will output the resulting sum bit and carry bit, and the process will continue until all the digits have been added. 

The values for the outputs are determined from the arithmetic sum of the three inputs. When all the input bits are 0, the outputs are 0. The S output is equal to 1 when only one input is equal to 1 or hence all three inputs are equal to 1. 

A full adder can be implemented in many different ways such as with a custom transistor-level circuit or composed of other gates. One example implementation is with 

In this implementation, the final OR gate before the carry-out output may be replaced by an XOR gate without altering the resulting logic. Using only two types of gates is convenient if the circuit is being implemented using simple IC chips which contain only one gate type per chip. In this light, C_out can be implemented as

 .

A full adder can be constructed from two half adders by connecting A and B to the input of one half adder, connecting the sum from that to an input to the second adder, connecting C_i to the other input and OR the two carry outputs. Equivalently, S could be made the three-bit XOR of A, B, and C_i, and C_out could be made the three-bit majority function of A, B, and C_i.

Schematic symbol for a 1-bit full adder with C_in and C_out  

By: Dinah Rose Y Galiza

SEVEN SEGMENT DISPLAY

A seven-segment display (SSD), is a form of electronic display device for displaying decimal numerals that is an alternative to the more complex dot matrix display displays. Seven-segment displays are widely used in digital clocks, electronic meters, and other electronic devices for displaying numerical information.

The segments of a 7-segment display are referred to by the letters A to G, as shown to the right, where the optional decimal point (an "eighth segment") is used for the display of non-integer numbers.

A seven segment display, as its name indicates, is composed of seven elements. Individually on or off, they can be combined to produce simplified representations of the arabic numerals. 

  

In a simple LED package, typically all of the cathodes (negative terminals) or all of the anodes (positive terminals) of the segment LEDs are connected and brought out to a common pin; this is referred to as a "common cathode" or "common anode" device. 

Common cathode has all the cathodes of the 7-segments connected directly together and the common anode has all the anodes of the 7-segments connected together.  The anode of a device is the terminal where current flows in from outside. The cathode of a device is the terminal where current flows out.

TRUTH TABLE ON HOW TO IMPLEMENT A SEVEN SEGMENT DISPLAY

COMPARATORS

A common arithmetic requirement is to compare two numbers, producing an indication if they are equal or if one is larger than the other. The Exclusive-OR produces a 1 if the two inputs are unequal and a 0, otherwise. Multibit numbers are unequal if any of the input pairs are unequal.  The output of the NOR is 1 if he number are equal. We accomplished the same thing with Exclusive- NORs and an AND gate.

4-BIT COMPARATORS

EXCLUSIVE OR

EXCLUSIVE NOR

These comparators can be extended to any number of bits.

          To build a 4 bit comparator that will indicate greater than and less than, as well as equal to, we recognize that starting at the most significant bit,

This can, of course, be exerted to any size, or 4 bit comparator can be cascaded, passing on the tree signals, greater then, less than, and equal to.

A TYPICAL  BIT OF A COMPARATOR

By: Dinah Rose Y Galiza

DECODERS

Decoder is a device that, when activated,  selects one of several output lines based on  coded input signal.Most commonly the input is in n- bit binary number, and there are 2^n output lines. Some decoders have an enable signal that activates it.

Active high decoder is the active output is 1 and the inactive ones are 0 and its truth table has two inputs and four outputs. The inputs are treated as a binary number and the output selected is made. This decoder consist oof an AND gate for each output plus NOT gate to invert the inputs.

                     a.)        an active high decoder                        

An active low output version of the decoder has one 0 corresponding to the input combination, the remaining outputs are 1. The circuit and the truth table describing it in the figure where the AND gates in the active high are just replaced by NANDs.

                b.)          an active low decoder

By: Dinah Rose Y Galiza